Rainbow Electronics AT89C5122 User Manual

Page 123

Advertising
background image

123

AT8xC5122/23

4202E–SCR–06/06

Reset Value = 0000 0000b

Table 73. USB Endpoint FIFO Reset Register - UEPRST (S:D5h)

7

6

5

4

3

2

1

0

-

EP6RST

EP5RST

EP4RST

EP3RST

EP2RST

EP1RST

EP0RST

Bit

Number

Bit

Mnemonic Description

7

-

Reserved
The value read from these bits is always 0. Do not change this bit.

6

EP6RST

Endpoint 6 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.

5

EP5RST

Endpoint 5 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.

4

EP4RST

Endpoint 4 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.

3

EP3RST

Endpoint 3 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.

2

EP2RST

Endpoint 2 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.

1

EP1RST

Endpoint 1 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.

0

EP0RST

Endpoint 0 FIFO Reset
Set this bit and reset the endpoint FIFO prior to any other operation, upon
hardware reset or when an USB bus reset has been received.
Then, clear this bit to complete the reset operation and start using the FIFO.

Advertising