Rainbow Electronics AT89C5122 - Manual (Page 20)

20
AT8xC5122/23
4202E–SCR–06/06
Memory Organization
The AT8xC5122/23 devices have separated address spaces for Program and Data
Memory, as shown in Figure 13 on page 29, Figure 14 on page 31 and Figure 15 on
page 32. The logical separation of Program and Data memory allows the Data Memory
to be accessed by 8-bit addresses, which can be more quickly stored and manipulated
by an-bit CPU. Nevertheless, 16-bit Data Memory addresses can also be generated
through the DPTR register.
Program Memory
Managament Depending on the state of EA pin, the MCU fetches the code from internal or external
program memory (ROMless mode)
Warning : the EA pin can not be left floating, otherwise MCU may have an unpredict-
able behaviour.
If EA is strapped to VCC, the MCU fetches the code from the internal program memory.
The way the MCU works in this mode depends on the device version. See next para-
graphs for further details.
If the EA is strapped to GND, the MCU fetches the code from external program memory.
This mode is common for all device versions wich supports it. After reset, the CPU
begins the execution from location 0000h. There can be up to 64 KBytes of program
memory. In this mode, the internal program memories are disabled.
The hardware configuration for external program execution is shown in Figure 9.
Figure 9. Executing from External Program Memory
Note that the 16 I/O lines (Ports 0 and 2) are dedicated to bus functions during external
Program Memory fetches. Port 0 serves as a multiplexed address/dat bus. It emits the
low byte of the Program Counter (PCL) as an address, and then goes into a float state
awaiting the arrival of the code byte from the Program Memory. During the time that the
low byte of the Program Counter is valid on P0, the signal ALE (Address Latch Enable)
clocks the byte into an address latch. Meanwhile, Port 2 emits the high byte of the Pro-
gram Counter (PCH). Then PSEN strobes the External Program Memory and the code
byte is read into the MCU.
PSEN is not activated and Ports P0 and P2 are not affected during internal program
fetches.
EXTERNAL PROGRAM
MEMORY AT8xC5122
P2
P0
AD7:0
A15:8
A7:0
A15:8
D7:0
A7:0
ALE
Latch
OE PSEN#