Rainbow Electronics AT89C5122 - Manual (Page 88)

88
AT8xC5122/23
4202E–SCR–06/06
Reset Value = 0X10 1111b (default value for a divider by two)
DC/DC Converter The Smart Card voltage (CVCC) is supplied by the integrated DC/DC converter which is
controlled by several registers:
• The SCICR register (Table 44 on page 79) controls the CVCC level by means of bits
VCARD[1:0].
• The SCCON register (Table 45 on page 80) enables to switch the DC/DC converter
on or off by means of bit CARDVCC.
• The DCCKPS register (Table 61 on page 94) controls the DC/DC clock and current.
The DC/DC converter cannot be switched on while the CPRES pin remains inactive. If
CPRES pin becomes inactive while the DC/DC converter is operating an automatic shut
down sequence of the DC/DC converter is initiated by the electronics.
It is mandatory to switch off the DC/DC Converter before entering in Power-down mode.
Configuration The DC/DC Converter can work in two different modes which are selected by bit MODE
in DCCKPS register:
• Pump Mode: an external inductance of 10 µH must be connected between pins LI
and VCC. VCC can be higher or lower than CVCC.
• Regulator mode : no external inductance is required but VCC must be always higher
than CVCC+0.3V. The Regulation mode will work even if an external inductance of
10 µH is connected between pins LI and VCC
The DC/DC clock prescaler which is controlled by bits DCCKPS[3:0], in DCCKPS regis-
ter must be configured to set the DC/DC clock to a working frequency of 4 MHz which
depends upon the value of the crystal. There is no need to change the default configura-
tion set by the reset sequence if an 8 MHz crystal is used by the application.
The DC/DC Converter implements a current overflow controller which avoids permanent
damage of the DC/DC converter in case of short circuit between CVCC and CVSS. The
maximum limit is around 100 mA. It is possible to increase this limit in normal operating
Table 59. Smart Card Clock Reload Register - SCICLK (S:C1h, SCRS=1)
7 6 5 4 3 2 1 0
XTSCS - SCICLK5 SCICLK4 SCICLK3 SCICLK2 SCICLK1 SCICLK0
Bit Number Bit Mnemonic Description
7 XTSCS
Smart Card Clock Selection Bit
If XTSCS bit is set OR EXT48 bit is set (in PLLCON register) , CK_PLL is used to generate CK_ISO.
Otherwise, CK_XTAL1 is used to generate CK_ISO.
See the Clock Tree diagram figure 17.
6 -
Reserved
The value read from this bit is indeterminate. Do not change these bits.
5 - 0 SCICLK[5:0]
SCIB clock reload register
Prescaler 2 reload value is used to defines the card clock frequency.
If SCICLK[5:0] is smaller than 48 :
Fck_iso = Fck_pll or Fck_XTAL1/ (2 * (48 - SCICLK[5:0]))
If SCICLK[5:0] is equal to 48 :
Fck_iso = Fck_XTAL1
SCICLK[5:0] must be smaller than 49.