IAI America MSEP - Manual (Page 135)

3.4 Fieldbus
Type
Address Map
127
(1) PLC Address Composition
(m is PLC input and output top word address for each axis number)
PLC ĺ MSEP (PLC Output) MSEP ĺ PLC (PLC Input)
A2 to A17 m B2 to B17 m
A18 to A33 m+1 B18 to B33 m+1
[Refer to Section 3.4.2 for the address maps for each Fieldbus.]
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(2) Input and Output Signal Assignment for each Axis
The I/O signals for each axis consists of 1-word for each I/O bit register.
Ɣ The I/O bit register is controlled using the ON/OFF signal in units of bit.
(ON = Applicable bit is “1”, OFF = Applicable bit is “0”)
Ɣ Pin Numbers A2 to A33 and B2 to B13 are assigned for each bit signal, which are equivalent
to the case when using PIO, because the contents of signals vary depending on the selection
of PIO pattern.
[Refer to 3.5 Control Signals for PIO Operation for the relation between pin numbers and
signals.]

PLC Output (m is PLC input and output top word address for each axis number)
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Address m
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Controller Input
Port (Pin) No.
A
17
A
16
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
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Address m+1
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
Controller Input
Port (Pin) No.
A
33
A
32
A
31
A
30
A
29
A
28
A
27
A
26
A
25
A
24
A
23
A
22
A
21
A
20
A
19
A
18
PLC Input (m is PLC input and output top word address for each axis number)
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Address m
F E D C B A 9 8 7 6 5 4 3 2 1 0
Controller Output
Port No.
B
17
B
16
B
15
B
14
B
13
B
12
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
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Address m+1
F E D C B A 9 8 7 6 5 4 3 2 1 0
Controller Output
Port No.
B
33
B
32
B
31
B
30
B
29
B
28
B
27
B
26
B
25
B
24
B
23
B
22
B
21
B
20
B
19
B
18
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1 word = 16 bit