Cirrus Logic CS8952 - Manual (Page 41)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 41
DS206F1
6.9 Interrupt Mask Register - Address 10h
This register indicates which events will cause an interrupt event on the MII_IRQ pin. Each bit acts as
an enable to the interrupt. Thus, when set, the event will cause the MII_IRQ pin to be asserted. When
clear, the event will not affect the MII_IRQ pin, but the status will still be reported via the Interrupt Sta-
tus Register (address 11h).
15 14 13 12 11 10 9 8
CIM Link
Unstable Link Status
Change
Descrambler
Lock Change
Premature End
Error
DCR
Rollover
FCCR
Rollover
RECR
Rollover
Remote
Loopback
Fault
7 6 5 4 3 2 1 0
Reset
Complete
Jabber
Detect
Auto-Neg
Complete Parallel
Detection Fault
Parallel
Fail
Remote
Fault
Page
Received
Reserved
BIT NAME TYPE RESET DESCRIPTION
15 CIM Link Unstable Read/Write 0 When set, an interrupt will be generated if an unsta-
ble link condition is detected by the Carrier Integrity
Monitor function.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
14 Link Status Change Read Write 1 When set, an interrupt will be generated each time
the CS8952 detects a change in the link status.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
13 Descrambler Lock
Change Read/Write 0 When set, an interrupt will be generated each time
the 100BASE-TX receive descrambler loses or
regains synchronization with the far-end.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
12 Premature End
Error Read/Write 0 When set, an interrupt will be generated when two
consecutive IDLES are detected in a 100BASE-TX
frame without the ESD sequence.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.