Cirrus Logic CS8952 - Manual (Page 57)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 57
DS206F1
2 Link Error Report
Enable Read/Write 0 When set, this bit causes link errors to be reported by
a value of 3h on RXD[3:0] and the assertion of
RX_ER. When clear, link errors are not reported
across the MII.
1 Packet Error Report
Enable Read/Write 0 When set, this bit causes packet errors to be
reported by a value of 2h on RXD[3:0] and the asser-
tion of RX_ER. When clear, packet errors are not
reported across the MII.
0 Code Error Report
Enable Read/Write 0 When set, code errors are reported and transmitted
on RXD[3:0].
When clear, this bit enables the Code Error Report
values on RXD[3:0] as selected by the Code Error
Report Select bit and also causes the assertion of
TX_ER to transmit a HALT code group.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
BIT NAME TYPE RESET DESCRIPTION