Cirrus Logic CS8952 - Manual (Page 52)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 52
DS206F1
6.16 PCS Sub-Layer Configuration Register - Address 17h
15 14 13 12 11 10 9 8
NRZI Enable
Time-Out
Select
Time-Out
Disable
Repeater
Mode
LED5 Mode Unlock Regs
MR Preamble
Enable
Fast Test
7 6 5 4 3 2 1 0
CLK25 Disable Enable LT/100 CIM Disable Tx Disable Rx Disable LED1 Mode LED4 Mode Digital Reset
BIT NAME TYPE RESET DESCRIPTION
15 NRZI Enable Read/Write 1 When this bit is set, the NRZI encoder and decoder
are enabled. When this bit is clear, NRZI encoding
and decoding are disabled.
14 Time-Out Select Read/Write 0 When this bit is set, the time-out counter in the
receive descrambler is set to time-out after 2 ms
without IDLES. When clear the counter is set to time-
out after 722
µs without IDLES.
13 Time-Out Disable Read/Write 0 When this bit is set, the time-out counter in the
receive descrambler is disabled. When this bit is
clear, the time-out counter is enabled.
12 Repeater Mode Read/Write Reset to the value
on the
REPEATER pin.
This bit defines the mode of the Carrier Sense (CRS)
signal. When this bit is set, CRS is asserted due to
receive activity only. When this bit is clear, CRS is
asserted due to either transmit or receive activity.
11 LED5 Mode Read/Write 0 This bit defines the mode of Pin LED5. When this bit
is set, pin LED5 indicates the synchronization status
of the 100BASE-TX descrambler. When this bit is
clear, LED5 indicates a collision.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.
10 Unlock Regs Read/Write 0 When set, this bit unlocks certain read only control
registers for factory testing. Leave clear for proper
operation.
Note: This bit is disabled, and writes to this bit are
ignored when the National Compatibility Mode bit of
the 10BASE-T Configuration Register (address 1Ch)
is set.