Cirrus Logic CS8952 - Manual (Page 78)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 78
DS206F1
RESET - Reset. Input, Pin 15.
This active high input initializes the CS8952, and causes the CS8952 to latch the input signal on the
following pins: COL/PHYAD0, CRS/PHYAD2, RX_ER/PHYAD4/RXD4, 10BT_SER, BP4B5B, BPALIGN,
BPSCR, ISODEF, REPEATER, RXD[1]/PHYAD1, and RXD[3]/PHYAD3.
XTAL_I - Crystal Input, Pin 96.
XTAL_O - Crystal Output, Pin 97.
A 25 MHz crystal should be connected across pins XTAL_I and XTAL_O. If a crystal is not used, a
25 MHz CMOS level clock may be connected to XTAL_I and XTAL_O left open.
NOTE: The XTAL_I pin capacitive load may be as high as 35pF. Any external clock source connected to this
pin must be capable of driving larger capacitive loads.
RSVD - Reserved. Pins 74, 75, 76, 77, 84, 98, and 99.
These seven pins are reserved and should be tied to VSS.
VDD_MII - MII Power. Pins 21, 34, and 66.
These pins provide power to the CS8952 MII interface. Typically VDD_MII will be either +5V or +3.3V.
VDD - Core Power. Pins 2, 11, 19, 40, 54, 79, 82, 88, 89, 94, and 100.
These pins provide power to the CS8952 core. Typically, VDD should be +5V.
VSS - Ground. Pins 1, 3, 10, 12, 13, 18, 20, 22, 35, 39, 41, 53, 55, 65, 78, 83, 85, 87, 90, 93, and 95.
These pins provide a ground reference for the CS8952.