Cs8952 – Cirrus Logic CS8952 User Manual
Page 60
CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
60
DS206F1
6.19
10BASE-T Status Register - Address 1Bh
15
14
13
12
11
10
9
8
Reserved
Polarity OK
10BASE-T
Serial
Reserved
7
6
5
4
3
2
1
0
Reserved
BIT
NAME
TYPE
RESET
DESCRIPTION
15:11 Reserved
Read Only
0 0000
10
Polarity OK
Read Only
0
When high, the polarity of the receive signal (at the
RXD+/RXD- inputs) is correct. If clear, the polarity is
reversed. If the Polarity Disable bit of 10BASE-T
Configuration Register (address 1Ch) is clear, then
the polarity is automatically corrected, if needed. The
Polarity OK status bit shows the true state of the
incoming polarity independent of the Polarity Disable
bit.
9
10BASE-T Serial
Read/Write Reset to the value
on the 10BT_SER
pin.
When set, this bit selects 10BASE-T serial mode.
When low, this bit selects 10BASE-T nibble mode.
This bit will only affect the CS8952 if it has been con-
figured for 10 Mb/s operation.
8:0
Reserved
Read Only
0 0000 0000