Cirrus Logic CS8952 - Manual (Page 58)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 58
DS206F1
6.18 Self Status Register - Address 19h
15 14 13 12 11 10 9 8
Link OK
Power
Down
Receiving
Data
Descrambler
Lock
Disable CRS
on Time-out
Auto-Neg
Enable Status
PAUSE FEFI Enable
7 6 5 4 3 2 1 0
Full Duplex
10BASE-T
Mode
CIM Status PHY Address
BIT NAME TYPE RESET DESCRIPTION
15 Link OK Read Only 0 When set, this bit indicates that a valid link connec-
tion has been detected. The type of link established
may be determined from bits 6, 7, and 9. When clear,
this bit indicates that a valid link connection does not
exist. This bit may be used to determine the current
status of the link.
14 Power Down Read Only 1 When high, this bit indicates that the CS8952 is in a
low power state.
13 Receiving Data Read Only 0 This bit is high whenever the CS8952 is receiving
valid data. It is a direct copy of the state of the
RX_DV pin accessible by software.
12 Descrambler Lock Read Only 0 When high, this bit indicates that the descrambler
has successfully locked to the scrambler seed of the
far-end transmitter and is able to descramble
received data.
11 Disable CRS on
Time-out Read/Write Reset to the logic
inverse of the
value on the
REPEATER pin.
This bit controls the state of the CRS pin upon a
descrambler time-out. When set, CRS will be forced
low upon a descrambler time-out, and will not be
released until the descrambler has re-acquired syn-
chronization.
10 Auto-Neg Enable
Status Read Only If auto-negotiation
is enabled via the
AN[1:0] pins, reset
to 1; otherwise,
reset to 0. This bit reflects the value of bit 12 in the Basic Mode
Control Register (address 00h). When set, it indi-
cates that auto-negotiation has been enabled. When
clear, this bit indicates that the mode of the CS8952
has been forced to that indicated by bits 6, and 7.
9 PAUSE Read Only 0 When set, this bit indicates that the Flow-Control
PAUSE function has been negotiated. This indicates
that both the local device and the link partner have
advertised this capability.
8 FEFI Enable Read/Write 0 This bit controls the Far-End Fault Generate and
Detect state machines. When this bit is set and auto-
negotiation is disabled (bit 10 is clear), both state
machines are enabled. When clear, this bit disables
both state machines.
7 Full Duplex Read Only If a full duplex
mode is enabled
via the AN[1:0]
pins, reset to 1;
otherwise, reset to
0. When set, this bit indicates that the CS8952 has
been configured for Full-Duplex operation.
6 10BASE-T Mode Read Only 0 When set, this bit indicates that the CS8952 has
been configured for 10 Mb/s operation.