Cirrus Logic CS8952 - Manual (Page 77)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 77
DS206F1
TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60.
These three-level pins allow adjustment to the rise and fall times of the 10BASE-TX transmitter output
waveform. The rise and fall times are symmetric.
Media Interface Pins
RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92.
Differential input pair receives 10 or 100 Mb/s data from the receive port of the transformer primary.
TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81.
Differential output pair drives 10 or 100 Mb/s data to the transmit port of the transformer primary.
RX_NRZ+, RX_NRZ- - FX Receive. Differential Input Pair, Pins 6 and 7.
PECL output pair receives 100 Mb/s NRZI-encoded data from an external optical module.
SIGNAL+, SIGNAL- - Signal Detect. Differential Input Pair, Pins 9 and 8.
PECL input pair receives signal detection indication from an external optical module.
TX_NRZ+, TX_NRZ- - FX Transmit. Differential Output Pair, Pins 5 and 4.
PECL output pair drives 100 Mb/s NRZI-encoded data to an external optical module.
General Pins
CLK25 - 25 MHz Clock. Output, Pin 17.
A 25 MHz Clock is output on this pin when the CS8952 is configured to use an external reference
transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode
Initialization pin (TCM) for more information on TX_CLK operating modes.
CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-layer
Configuration Register (address 17h).
RES - Reference Resistor. Input, Pin 86.
This input should be connected to ground with a 4.99 k
Ω +/-1% series resistor. The resistor is needed
for the biasing of internal analog circuits.
TXSLEW0 pin TXSLEW1 mode Rise/Fall time
low low 0.5 ns
low floating 1.0 ns
low high 1.5 ns
floating low 2.0 ns
floating floating 2.5 ns
floating high 3.0 ns
high low 3.5 ns
high floating 4.0 ns
high high 4.5 ns