Cirrus Logic CS8952 - Manual (Page 59)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 59
DS206F1
5 CIM Status Read Only 0 When clear, this bit indicates that a stable link con-
nection has been detected. When an unstable link is
detected and the Carrier Integrity Monitor Disable bit
in the PCS Sub-Layer Configuration Register
(address 17h) is clear, this bit is set and latched. It
will remain set until this register is read.
4:0 PHY Address Field Read/Write Reset to the val-
ues on the
PHYAD[4:0] pins.
The value on pins PHYAD[4:0] are latched into this
field at power-up or reset. These bits define the PHY
address used by the management layer to address
the PHY. The external logic must know this address
in order to select this particular CS8952’s registers
individually via the MDIO and MDC pins.
BIT NAME TYPE RESET DESCRIPTION