Cirrus Logic CS8952 - Manual (Page 74)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 74
DS206F1
ISODEF - Isolate Default. Input, Pin 63.
When asserted high during power-up or reset, the MII will power-up electrically isolated except for the
MDIO and MDC pins. When low, the part will exit reset fully electrically connected to the MII.
The MII may also be isolated under software control through bit 10 of the Basic Mode Control Register
(address 00h).
At power-up or at reset, the value on this pin is latched into bit 10 of the Basic Mode Control Register
(address 00h). This pin includes a weak internal pull-down (> 20 k
Ω), or the value may be set by an
external 4.7 k Ω pull-up or pull-down resistor.
LED1 - Transmit Active LED. Open Drain Output, Pin 69.
This active-low output indicates transmit activity. It contains a pulse stretcher to insure that the transmit
events are visible when the pin is used to drive an LED. The definition of this pin may be modified to
indicate Disconnect Detection (bit 5 of the Self Status Register (address 19h)) by setting bit 2 of the
PCS Sub-layer Configuration Register (address 17h).
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LED2 - Receive Activity LED. Open Drain Output, Pin 70.
This active-low output indicates receive activity. It contains a pulse stretcher to insure that the receive
events are visible when the pin is used to drive an LED.
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LED3 - Link Good LED. Open Drain Output, Pin 71.
This active-low output indicates the CS8952 has detected a valid link.
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LED4 - Polarity/Full Duplex LED. Open Drain Output, Pin 72.
This active-low output indicates:
1) for 100 Mb/s operation, the CS8952 is in full-duplex operation,
2) for 10 Mb/s operation, either good polarity exists or full duplex is selected (see bit 1 in the PCS Sub-
layer Configuration Register (address 17h)).
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LED5 - Collision/Descrambler Lock LED. Open Drain Output, Pin 73.
This active-low output is asserted when either the CS8952 detects a collision (bit 11 of the PCS Sub-
Layer Configuration Register (address 17h) is clear), or the 100BASE-TX descrambler is synchronized
(bit 11 of the PCS Sub-Layer Configuration Register (address 17h) is set). It contains a pulse stretcher
to insure that the collision events are visible when the pin is used to drive an LED.
This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin.
LPBK - Loopback Enable. Input, Pin 51.
When this pin is asserted high and the CS8952 is operating in 100 Mb/s mode, the CS8952 will perform
a local loopback inside the PMD block, routing the scrambled NRZI output to the NRZI input port on the
descrambler. The loopback includes all CS8952 100 Mb/s functionality except the MLT-3 coders and the
analog line interface blocks.
When asserted high and the CS8952 is operating in 10 Mb/s mode, the CS8952 will perform a local
ENDEC loopback.