Cirrus Logic CS8952 - Manual (Page 45)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 45
DS206F1
8 Remote Loopback
Fault Read Only 0 When set, this bit indicates that the Elastic Buffer has
detected an over-run or an under-run condition. In
any case, the frame generating this fault will be ter-
minated.
This should never happen since the depth of the
elastic buffer (10 bits) is greater than twice the maxi-
mum number of bit times the receive and transmit
clocks may slip during a maximum length packet
assuming clock frequency tolerances of 100 ppm or
less.
7 Reset Complete Read Only 0 When set, this bit indicates that the internal analog
calibration cycle has completed, and all analog and
digital circuitry is ready for normal operation.
6 Jabber Detect Read Only 0 In 10BASE-T mode, if the last transmission is longer
than 105 ms, then the packet output is terminated by
the jabber logic and this bit is set.
This bit is implemented with a latching function so
that the occurrence of a jabber condition causes it to
become set until it is cleared by a read to this regis-
ter, a read to the Basic Mode Status Register
(address 01h), or a reset.
No jabber detect function has been defined for
100BASE-TX.
This bit is the same as in the Basic Mode Status Reg-
ister (address 01h).
5 Auto-Neg Complete Read Only 0 This bit is set when the auto-negotiation process has
completed. This is an indication that the Auto-Negoti-
ation Advertisement Register (address 04h), the
Auto-Negotiation Link Partner Ability Register
(address 05h), and the Auto-Negotiation Expansion
Register (address 06h) are valid.
This bit is the same as in the Basic Mode Status Reg-
ister (address 01h).
4 Parallel Detection
Fault Read Only 0 When set, this bit indicates an error condition in
which auto-negotiation has detected that unstable
10BASE-T or 100BASE-TX link signalling was
received. This bit is self-clearing.
This bit is the same as in the Auto-Negotiation
Expansion Register (address 06h)
3 Parallel Fail Read Only 0 When set, this bit indicates that a parallel detection
has occurred for a technology that is not currently
advertised by the local device.
BIT NAME TYPE RESET DESCRIPTION