Cirrus Logic CS8952 - Manual (Page 68)

CS8952
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 68
DS206F1
MII Interface Pins
COL/PHYAD0 - Collision Detect/PHY Address 0. Input/Tri-State Output, Pin 48.
Asserted active-high to indicate a collision on the medium during half-duplex operation. In full-duplex
operation, COL is undefined and should be ignored. When configured for 10 Mb/s operation, COL is
also used to indicate a Signal Quality Error (SQE) condition.
At power-up or at reset, the logic value on this pin is latched into bit 0 of the PHY Address field of the
Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 k
Ω), or the value
may be set by an external 4.7 k
Ω pull-up or pull-down resistor.
CRS/PHYAD2 - Carrier Sense/PHY Address 2. Input/Tri-State Output, Pin 49.
The operation of CRS is controlled by the REPEATER pin as follows:
At power-up or at reset, the logic value of this pin is latched into bit 2 of the PHY Address Field of the
Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 k
Ω), or the value
may be set by an external 4.7 k
Ω pull-up or pull-down resistor.
MDC - Management Data Clock. Input, Pin 28.
Input clock used to transfer serial data on MDIO. The maximum clock rate is 16.67 MHz. This clock may
be asynchronous to RX_CLK and TX_CLK.
MDIO - Management Data Input/Output. Bi-Directional, Pin 27.
Bi-directional signal used to transfer management data between the CS8952 and the Ethernet controller.
In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled
high during power-up or reset, and the MDIO pin should have an external 1.5 k
Ω pull-up resistor. For
systems not required to drive external connectors and cables as described in the IEEE802.3u
specification, the external pull-up resistor may not be necessary.
MII_IRQ - MII Interrupt. Open Drain Output, Pin 26.
Asserted low to indicate the status corresponding to one of the unmasked interrupt status bits in the
Interrupt Status Register (address 11h) has changed. It will remain low until the ISR is read, clearing all
status bits.
This open drain pin requires a 4.7 k Ω pull-up resistor.
RX_CLK - Receive Clock. Tri-State Output, Pin 36
Continuous clock output used as a reference clock for sampling RXD[3:0], RX_ER, and RX_DV.
RX_CLK will have the following nominal frequency:
REPEATER pin DUPLEX mode CRS Indicates
high don’t care receive activity only
low full duplex receive activity only
low half duplex receive or transmit activity
Speed 10BT_SER pin Nominal frequency
100 Mb/s n/a 25 MHz
10 Mb/s low (parallel) 2.5 MHz
10 Mb/s high (serial) 10 MHz