Enabling compression before design compilation, Enabling compression after design compilation, Aes encryption – Altera MAX 10 FPGA User Manual

Page 41: Enabling compression before design compilation -11, Enabling compression after design compilation -11, Aes encryption -11

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• Before design compilation—using the Compiler Settings menu.

• After design compilation—using the Convert Programming Files option.

Enabling Compression Before Design Compilation

To enable compression before design compilation, follow these steps:
1. On the Assignments menu, click Device. The Settings dialog box appears.

2. Click Device and Pin Options. The Device and Pin Options dialog box appears.

3. Click the Configuration tab.

4. Turn on Generate compressed bitstreams.

5. Click OK.

6. In the Settings dialog box, click OK.

Related Information

Configuration Data Compression

on page 2-22

Enabling Compression After Design Compilation

To enable compression after design compilation, follow these steps:
1. On the File menu, click Convert Programming Files.

2. Under Output programming file, from the pull-down menu, select your desired file type.

3. If you select the Programmer Object File (.pof), you must specify a configuration device, directly

under the file type.

4. In the Input files to convert box, select SOF Data.

5. Click Add File to browse to the MAX 10 device family .sof.

6. In the Convert Programming Files dialog box, select the .pof you added to SOF Data and click

Properties.

7. In the SOF Properties dialog box, turn on the Compression option.

Related Information

Configuration Data Compression

on page 2-22

AES Encryption

This section covers detailed guidelines on applying AES Encryption for design security. There are two

main steps in applying design security in MAX 10 devices. First is to generate the encryption key

programming (

.ekp

) file and second is to program the

.ekp

file into the device.

The

.ekp

file has other different formats, depending on the hardware and system used for programming.

There are three file formats supported by the Quartus II software:
• JAM Byte Code (

.jbc

) file

• JAM

Standard Test and Programming Language (STAPL) Format (

.jam

) file

• Serial Vector Format (

.svf

) file

Only the

.ekp

file type generated automatically from the Quartus II software. You must create the

.jbc

,

.jam

and

.svf

files using the Quartus II software if these files are required in the key programming.

Note: Altera recommends that you keep the

.ekp

file confidential.

UG-M10CONFIG

2015.05.04

Enabling Compression Before Design Compilation

3-11

MAX 10 FPGA Configuration Design Guidelines

Altera Corporation

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