Altera dual configuration ip core references, Altera dual configuration ip core references -1 – Altera MAX 10 FPGA User Manual
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Altera Dual Configuration IP Core References
5
2015.05.04
UG-M10CONFIG
Altera Dual Configuration IP Core Avalon-MM Address Map
Table 5-1: Altera Dual Configuration IP Core Avalon-MM Address Map for MAX 10 Devices
• Altera recommends you to set the reserve bits to
0
for write operations. For read operations, the IP core will
always generate
0
as the output.
• Write
1
to trigger any operation stated in the description.
• You need to trigger the desired operation from offset 2 before any read operation of offset 4, 5, 6 and 7.
Offset
R/W
Width
(Bits)
Description
0
W
32
• Bit 0—trigger reconfiguration.
• Bit 1—reset the watchdog timer.
• Bit 31:2—reserved.
Signals are triggered at the same write cycle on Avalon.
1
W
32
• Bit 0—trigger
config_sel_overwrite
to the input register.
• Bit 1—writes
config_sel
to the input register. Set 0 or 1 to load
from configuration image 0 or 1 respectively.
• Bit 31:2—reserved.
The
busy
signal is generated right after the write cycle, while the
configuration image information is registered. Once
busy
signal is
high, writing to this address is ignored until the process is
completed and the
busy
signal is de-asserted.
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