Altera Phase-Locked Loop Reconfiguration IP Core - Manual (Page 4)

Page 4 Parameter Settings
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation
You can open a .mif in a text editor to make use of the comments embedded within
the file. These comments show you the scan chain values and positions based on your
design parameterization (see
Figure 1 ). If you open a .mif in the Quartus II software,
you can regenerate the .mif in the ALTPLL parameter editor to restore the comments.
f
For more information about implementing PLL reconfiguration in the supported
Stratix series, refer to
AN 282: Implementing PLL Reconfiguration in Stratix & Stratix GX
Devices, AN 367: Implementing PLL Reconfiguration in Stratix II Devices and AN 454:
Implementing PLL Reconfiguration in Stratix III Devices .
EDA
Specifies the libraries needed for functional simulation.
Generate netlist
Specifies whether to turn on the option to generate synthesis area and timing
estimation netlist.
Summary
Specifies the types of files to be generated. A gray checkmark indicates a file that is
automatically generated; a red checkmark indicates an optional file.
Choose from the following types of files:
■ AHDL Include file (<function name>.inc)
■ VHDL component declaration file (<function name>.cmp)
■ Quartus II symbol file (<function name>.bsf)
■ Instantiation template file (<function name>_inst.v or <function
name>_inst.vhd
■ Verilog HDL block box file (<function name>_bb.v)
If Generate netlist option is turned on, the file for that netlist is also available
(<function name>_syn.v).
Table 1. ALTPLL_RECONFIG Parameter Settings
Page Options Description
Figure 1. MIF file