Altera Phase-Locked Loop Reconfiguration IP Core - Manual (Page 27)

Design Example Page 27
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction February 2012 Altera Corporation
2. pll_reconfig_circuit:u2—This represents the PLL reconfiguration circuitry used
by the PLL to reconfigure its settings during user mode. In addition, this circuitry
has a scan-chain cache, which contains the intended PLL settings to be
reconfigured. It also has additional ports to take advantage of cycling multiple
.mif
files for reconfiguration from external ROMs. This design example
demonstrates the capability of these ports. The settings are represented by the
the_pll_initial.mif
file. The settings are as follows:
■ inclk
= 50 MHz
■ c0 = 100 MHz
3. rom_muxer:u3—This represents a 4-to-1 multiplexer used to multiplex serial data
coming from four ROMs to the rom_data_in port of the pll_reconfig_circuit
module. The multiplexer is used because the rom_data_in port is 1 bit in size;
however, it is controlled by a 2-bit selector, hence its ability to multiplex four
signals.
4. rom_1:u4—This represents the external ROM, which contains the intended
reconfiguration settings of the PLL. It has a 1-bit output port ( q ) because of the
serial nature of writing the intended PLL settings to the scan-chain cache of the
pll_reconfig_circuit
module. It has a capacity of 256 words of 1-bit size. The ROM
uses 256 words because that is the closest approximate size of the scan-chain file
for this type of PLL, which is 234 bits. For this ROM, it is represented by the
the_pll_200_mhz.mif
file, which is 234 bits. The settings are as follows:
■ inclk
= 50 MHz
■ c0
= 200 MHz
5. rom_2:u5—This represents the external ROM, which contains the intended
reconfiguration settings of the PLL. It has a 1-bit output port ( q ) because of the
serial nature of writing the intended PLL settings to the scan-chain cache of the
pll_reconfig_circuit
module. It has a capacity of 256 words of 1-bit size. The ROM
uses 256 words because that is the closest approximate size of the scan-chain file
for this type of PLL, which is 234 bits. For this ROM, it is represented by the
the_pll_300_mhz.mif
file, which is 234 bits. The settings are as follows:
■ inclk = 50 MHz
■ c0 = 300 MHz
6. rom_3:u6—This represents the external ROM, which contains the intended
reconfiguration settings of the PLL. It has a 1-bit output port ( q ) because of the
serial nature of writing the intended PLL settings to the scan-chain cache of the
pll_reconfig_circuit
module. It has a capacity of 256 words of 1-bit size. The ROM
uses 256 words because that is the closest approximate size of the scan-chain file
for this type of PLL, which is 234 bits. For this ROM, it is represented by the .mif
file the_pll_400_mhz.mif, which is 234 bits. The settings are as follows:
■ inclk = 50 MHz
■ c0
= 400 MHz