Simulation – Altera Phase-Locked Loop Reconfiguration IP Core User Manual
Page 6
Page 6
Simulation
Phase-Locked Loop Reconfiguration (ALTPLL_RECONFIG) Megafunction
February 2012
Altera Corporation
Simulation
You can perform functional and gate-level timing simulations of the megafunction.
f
For more information, refer to the appr
section in
volume 3 of the Quartus II Handbook.
If phase-shifting occurs after a PLL reconfiguration, use gate-level timing simulation
instead of functional simulation to verify the correct counter settings and phase shifts.
For non-zero PLL phase shifts, the frequency of the output clocks after a
reconfiguration is correct, but the phase may be incorrect. If the phase shift is
significant, use gate-level timing simulation to verify the timing behavior.
Functional Description—Implementing Multiple Reconfiguration Using
an External ROM
The ALTPLL_RECONFIG megafunction allows you to reconfigure the PLL using an
external ROM with multiple configuration files. With this feature, you can perform
the following:
■
Specify an external ROM and feed its content to the ALTPLL_RECONFIG
megafunction.
■
Use the megafunction with multiple PLL configuration settings that are stored in
configuration files during user mode.
■
Use the megafunction with applications that require flexible dynamic-shifting of
PLL settings during user mode.
■
Reconfigure the initial PLL settings from a source other than an embedded
random-access memory (RAM), such as an off-chip flash device, which is useful in
HardCopy-type applications.
1
This feature is available for Stratix III, Stratix IV, Cyclone III, Cyclone IV,
HardCopy III, HardCopy IV, and Arria II GX devices only.
To support reconfiguration from multiple configuration files, the
ALTPLL_RECONFIG megafunction has three input ports and two output ports:
■
The
write
_
from
_
rom
input port signals the ALTPLL_RECONFIG megafunction
instantiation to write to the scan cache from the ROM.
■
The
rom
_
data
_
in
input port holds data from the ROM.
■
The
reset
_
rom
_
address
input port lets you restart the read process from the ROM.
The data arrives serially from the ROM, starting from bit 0.
■
The
rom
_
address
_
out
output bus holds the current address of the ROM data to be
written to the scan cache.
■
The
write
_
rom
_
ena
output port enables the intended ROM to be read out.