Altera Embedded Systems Development Kit, Cyclone III Edition - Manual (Page 11)

1–5 Development Board Version 1.0. Altera Corporation
Altera Embedded Systems Development Kit, Cyclone III Edition July 2010
About the Development Board
• For debugging software via a trace pod or oscilloscope
● USB connector
• For USB 2.0 interface development with soft USB MAC IP
and an external PHY
● SD Card connector
• For SD Card interface development
● Santa Cruz Header
• For connecting to a custom prototype board or any one of
accessory partner boards
1
The Altera Embedded Systems Development Kit, Cyclone III
edition has HSMC as well as Santa Cruz connectors. As a result
it can be used with any one of the many accessory boards to suite
wide range of applications available from Altera’s development
kit partners.
For a full list of accessory boards that connect via the HSMC and Santa
Cruz interfaces visit
http://www.altera.com/products/devkits/kit-
daughter_boards.jsp
Factory design: the Application Selector
On the Cyclone III FPGA base board resides the Cyclone III 3C120 FPGA
which configures from flash with a factory processor system, running a
software application called Application Selector. The application selector
allows users to configure the kit from designs stored on SD Card via the
LCD Color Touch Panel or from designs stored on your local PC via an
Ethernet connection. The application selector design is provided in full
source form to serve as a stating point for your embedded system
development.
Max II CPLD on the Cyclone III FPGA
The Max II CPLD on the Cyclone III FPGA base board is responsible for
configuring the FPGA on power up with the contents of the Flash, i.e. the
Application Selector factory image. The default mode of configuration is
Fast Passive Parallel.
Max II CPLD on LCD Multimedia HSMC
On the LCD Multimedia HSMC resides a MAX II CPLD whose function
is to relay data and control signals to the various peripheral devices as
shown in the
Figure 1–1 .
The MAX II CPLD performs voltage translation and de-multiplexing of
video pipeline signals to the LCD HSMC Touch panel. The video pipeline
signals have been multiplexed inside the FPGA and de-multiplexed by