Altera Embedded Systems Development Kit, Cyclone III Edition - Manual (Page 44)

Altera Corporation Development Board Version 1.0. 6–6
July 2010 Altera Embedded Systems Development Kit, Cyclone III Edition
Example Processor Systems
■ SD Card
● The controller, API, and FAT File System for the SD-Card used
in the Nios II LCD System is provided under license agreement
by SLS (
http://www.slscorp.com )
● The example processor system contains the SD MMC SPI CORE
which is a component that has been provided by a third party
vendor, SLS in encrypted format. To compile this core in your
SOPC Builder system, you will need to get a license from SLS.
However, if your particular application has no need to access the
SD Card then you do not need to include the SD Card core in
your system. Simply uncheck this core or delete it and re-
generate the system. You should now be able to rebuild the
hardware system without error.
Communication Interfaces
■ Ethernet MAC
● 10/100 Ethernet connection for the Ethernet port on the LCD
Multimedia HSMC
■ JTAG UART
● Used for Serial communication and debugging Nios II
applications via the on-board USB-Blaster circuitry.
■ UART
● Serial communication link for general purpose communications
and debug.
Peripheral Set
■ PLL
● Accepts the global input clock source from the 50MHz on-board
oscillator and generates the following clocks
• 100 MHz CPU Clock
• 100 MHz SSRAM Clock
• 66.5 MHz DDR SDRAM Clock
• 60 MHz Peripheral Clock (“slow peripherals”)
• 40 MHz Remote System Update Clock
■ System Clock Timer
● General purpose system timer.
■ Performance Counter
● Counter used for debug and system performance analysis.
■ System ID
● Used to sync the hardware system generation with the software
generation tools.
■ Max II Interface
● Communicates with the Max II CPLD on the base board. The
Max II CPLD manages configuration of the FPGA on boot up
using Fast Passive Parallel (FPP) configuration scheme.