Altera Cyclone III LS FPGA Development Board - Manual (Page 19)

Chapter 2: Board Components 2–11
Configuration, Status, and Setup Elements
© October 2009 Altera Corporation Cyclone III LS FPGA Development Board Reference Manual
Configuration, Status, and Setup Elements
This section describes the board's configuration, status, and setup elements.
Configuration
This section describes the FPGA, flash memory, and MAX II CPLD EPM2210 System
Controller device programming methods supported by the Cyclone III LS FPGA
development board. The Cyclone III LS FPGA development board supports the
following three configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ Flash memory download is used for storing FPGA images which the MAX II
CPLD EPM2210 System Controller uses to configure the Cyclone III LS device
either on board power up or after the the PGM configure push-button switch (S8)
is pressed.
■ External USB-Blaster for configuring the FPGA using an external USB-Blaster.
FPGA Programming over Embedded USB-Blaster
The USB-Blaster is implemented using a USB Type-B connector (J4), a FTDI USB 2.0
PHY device (U11), and an Altera MAX IIZ CPLD (U13). This allows the configuration
of the FPGA using a USB cable directly connected between the USB port on the board
(J4) and a USB port of a PC running the Quartus II software. The JTAG chain is
normally mastered by the embedded USB-Blaster found in the MAX
IIZ CPLD
EPM240Z.
The embedded USB-Blaster is automatically disabled when an external USB-Blaster is
connected to the JTAG chain.
Figure 2–4 illustrates the JTAG chain.