Altera Cyclone III LS FPGA Development Board - Manual (Page 48)

2–40 Chapter 2: Board Components
Memory
Cyclone III LS FPGA Development Board Reference Manual © October 2009 Altera Corporation
U14.A1 Address bus FSM_A22
2.5-V
AB16
U14.B11 Address bus FSM_A23 AE13
U14.C10 Address bus FSM_A24 AG11
U14.P2 Address bus FSM_A25 AE9
U14.J10 Data bus FSM_D0 AH9
U14.J11 Data bus FSM_D1 AH24
U14.K10 Data bus FSM_D2 AF25
U14.K11 Data bus FSM_D3 AE5
U14.L10 Data bus FSM_D4 AB11
U14.L11 Data bus FSM_D5 AD24
U14.M10 Data bus FSM_D6 AF9
U14.M11 Data bus FSM_D7 AE7
U14.D10 Data bus FSM_D8 AE23
U14.D11 Data bus FSM_D9 AF15
U14.E10 Data bus FSM_D10 AD17
U14.E11 Data bus FSM_D11 AF20
U14.F10 Data bus FSM_D12 AH25
U14.F11 Data bus FSM_D13 AE18
U14.G10 Data bus FSM_D14 AD6
U14.G11 Data bus FSM_D15 AG20
U14.D1 Data bus FSM_D16 AH20
U14.D2 Data bus FSM_D17 AH18
U14.E1 Data bus FSM_D18 AF8
U14.E2 Data bus FSM_D19 AE20
U14.F1 Data bus FSM_D20 AB19
U14.F2 Data bus FSM_D21 AB10
U14.G1 Data bus FSM_D22 AC17
U14.G2 Data bus FSM_D23 AD10
U14.J1 Data bus FSM_D24 AG9
U14.J2 Data bus FSM_D25 AE21
U14.K1 Data bus FSM_D26 AD22
U14.K2 Data bus FSM_D27 AH23
U14.L1 Data bus FSM_D28 AG5
U14.L2 Data bus FSM_D29 AB9
U14.M1 Data bus FSM_D30 AD9
U14.M2 Data bus FSM_D31 AD16
U14.A8 Address status controller SRAM_ADSCn AH19
U14.B9 Address status processor SRAM_ADSPn AB18
U14.A9 Address valid SRAM_ADVn AB20
Table 2–40. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board Reference Description Schematic Signal Name I/O Standard
Cyclone III LS Device
Pin Number