Altera Transceiver Signal Integrity Development Kit, Stratix IV GX Edition - Manual (Page 19)

Chapter 2: Board Components 2–9
Configuration, Status, and Setup Elements
November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,
Stratix IV GX Edition Reference Manual
Configuration, Status, and Setup Elements
This section describes the board’s configuration, status, and setup elements.
Configuration
The Stratix IV GX transceiver signal integrity development board supports three
configuration methods:
■ Embedded USB-Blaster is the default method for configuring the FPGA at any
time using the Quartus II Programmer in JTAG mode with the supplied USB cable.
■ MAX II+Flash FPP download for configuring the FPGA using stored images from
the flash on either power-up or pressing the reset push button (SW8).
■ JTAG programming header (J28) for configuring the FPGA using an external
USB-Blaster (not supplied) and the Quartus II Programmer.
The following sections describe each of these methods.
Embedded USB-Blaster
Figure 2–3 shows the block diagram for the embedded USB-Blaster. The USB-Blaster
is implemented using a Type-B USB connector (CN1), a Future Technologies FT245BL
USB PHY device (U16), and an Altera MAX7064 CPLD (U17). This allows
configuration of the FPGA using a USB cable directly connected between the USB port
on the board (CN1) and a USB port of a PC running the Quartus II software.
GXB2 Short Receive Channel Transceiver channel 2 7 in. Trace Length (8.5G)
GXB1 6 Full Duplex
Transceiver Channels
(One entire block)
Transceiver channel 24
Four Full Duplex channels from one entire
transceiver block (two from clock multiplier unit
(CMU) block)
Spares
Spare[7:0] 2.5-V CMOS inout 8 Spare signals to the MAX II CPLD
Total Device I/O: 208
Available Stratix IV GX I/O: 736
Table 2–4. Stratix IV GX I/O Usage Summary (Part 3 of 3)
Function I/O Type I/O Count Description