Research Concepts RC2000A - Manual (Page 66)

66 RC2000A Dual Axis Antenna Controller Appendix D RCI RS-422 Specification
A slave will exit State 2 and enter:
• State 3 (Slave Data State) if received address byte equals a slave's address.
• State 1 (Slave Idle State) if received address byte does not equal a slave's address.
• State 2 (remain in current state) if STX byte is received, which may be the beginning of
a new message data block.
State 3 (Slave Data State). In State 3, a slave is engaged in receiving the command and associated
data bytes sent by a master-controller.
A slave will exit State 3 and enter:
• State 4 (Slave Data Error State) if ETX byte is received signifying the end of data in the
message.
• State 1 (Slave Idle State) if invalid command, or data character, or incorrect number of
data bytes is received.
State 4 (Slave Data Error State). In State 4, a slave is waiting to receive a Checksum byte that tests the
transmitted message for errors.
A slave will exit State 4 and enter:
• State 5 (Command Execute State) if a Checksum byte is true -received LRC value of
Checksum byte equals the LRC value computed by a slave during message reception.
• State 1 (Slave Idle State) if a Checksum byte is false -- received LRC value of
Checksum byte does not equal the LRC value computed by a slave during message
reception.
State 5 (Command Execute State). In State 5, a slave, having completed reception of a message,
executes a function specified by a command byte. A slave will send an appropriate response message
to a master-controller after receiving the last character of the message.
A slave will always exit State 5 and enter Device Idle State, State 1.
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