Document Outline

• REVISION HISTORY
• Table of contents
• CHAPTER 1 CPU PROGRAMMIING MODEL
  • 1.1 CPU Register
  • 1.2 General-purpose Registers
  • 1.3 Control Registers
    • 1.3.1 Processor Status Word Register: PSW (CR0)
    • 1.3.2 Condition Bit Register: CBR (CR1)
    • 1.3.3 Interrupt Stack Pointer: SPI (CR2) User Stack Pointer: SPU (CR3)
    • 1.3.4 Backup PC: BPC (CR6)
    • 1.3.5 Floating-point Status Register: FPSR (CR7)
    • 1.3.6 Floating-point Exceptions (FPE)
  • 1.4 Accumulator
  • 1.5 Program Counter
  • 1.6 Data Format
    • 1.6.1 Data Type
    • 1.6.2 Data Format
  • 1.7 Addressing Mode
• CHAPTER 2 INSTRUCTION SET
  • 2.1 Instruction set overview
    • 2.1.1 Load/store instructions
    • 2.1.2 Transfer instructions
    • 2.1.3 Operation instructions
    • 2.1.4 Branch instructions
    • 2.1.5 EIT-related instructions
    • 2.1.6 DSP function instructions
    • 2.1.7 Floating-point Instructions
    • 2.1.8 Bit Operation Instructions
  • 2.2 Instruction format
• CHAPTER 3 INSTRUCTIONS
  • 3.1 Conventions for instruction description
  • 3.2 Instruction description
    • ADD
    • ADD3
    • ADDI
    • ADDV
    • ADDV3
    • ADDX
    • AND
    • AND3
    • BC
    • BCLR
    • BEQ
    • BEQZ
    • BGEZ
    • BGTZ
    • BL
    • BLEZ
    • BLTZ
    • BNC
    • BNE
    • BNEZ
    • BRA
    • BSET
    • BTST
    • CLRPSW
    • CMP
    • CMPI
    • CMPU
    • CMPUI
    • DIV
    • DIVU
    • FADD
    • FCMP
    • FCMPE
    • FDIV
    • FMADD
    • FMSUB
    • FMUL
    • FSUB
    • FTOI
    • FTOS
    • ITOF
    • JL
    • JMP
    • LD
    • LD24
    • LDB
    • LDH
    • LDI
    • LDUB
    • LDUH
    • LOCK
    • MACHI
    • MACLO
    • MACWHI
    • MACWLO
    • MUL
    • MULHI
    • MULLO
    • MULWHI
    • MULWLO
    • MV
    • MVFACHI
    • MVFACLO
    • MVFACMI
    • MVFC
    • MVTACHI
    • MVTACLO
    • MVTC
    • NEG
    • NOP
    • NOT
    • OR
    • OR3
    • RAC
    • RACH
    • REM
    • REMU
    • RTE
    • SETH
    • SETPSW
    • SLL
    • SLL3
    • SLLI
    • SRA
    • SRA3
    • SRAI
    • SRL
    • SRL3
    • SRLI
    • ST
    • STB
    • STH
    • SUB
    • SUBV
    • SUBX
    • TRAP
    • UNLOCK
    • UTOF
    • XOR
    • XOR3
• APPENDICES
  • Appendix1 Hexadecimal Instraction Code
  • Appendix 2 Instruction List
  • Appendix 3 Pipeline Processing
    • Appendix 3.1 Instructions and Pipeline Processing
    • Appendix 3.2 Pipeline Basic Operation
  • Appendix 4 Instruction Execution Time
  • Appendix 5 IEEE754 Specification Overview
    • Appendix 5.1 Floating Point Formats
    • Appendix 5.2 Rounding
    • Appendix 5.3 Exceptions
  • Appendix 6 M32R-FPU Specification Supplemental Explanation
    • Appendix 6.1 Operation Comparision: Using 1 instruction (FMADD or FMSBU) vs. two instructions (FMUL and FADD)
      • Appendix 6.1.1 Rounding Mode
      • Appendix 6.1.2 Exception occurring in Step 1
    • Appendix 6.2 Rules concerning Generation of QNaN in M32R-FPU
  • Appendix 7 Precautions
    • Appendix 7.1 Precautions to be taken when aligning data
• INDEX