Renesas M32R-FPU - Manual (Page 74)

3
3-36 M32R-FPU Software Manual (Rev.1.01)
INSTRUCTIONS
3.2 Instruction description
FADD FADD
[Mnemonic]
FADD Rdest,Rsrc1,Rsrc2
[Function]
Floating-point add
Rdest = Rsrc1 + Rsrc2 ;
[Description]
Add the floating-point single precision values stored in Rsrc1 and Rsrc2 and store the result in
Rdest. The result is rounded according to the RM field of FPSR. The DN bit of FPSR handles the
modification of denormalized numbers. The condition bit (C) remains unchanged.
[EIT occurrence]
Floating-Point Exceptions (FPE)
• Unimplemented Operation Exception (UIPL)
• Invalid Operation Exception (IVLD)
• Overflow (OVF)
• Underflow (UDF)
• Inexact Exception (IXCT)
[Encoding]
floating-point Instructions
Floating-point add
[M32R-FPU Extended Instruction]
src1 1101 src2 0000 dest 0000 0000 0000
FADD Rdest,Rsrc1,Rsrc2