Renesas M32R-FPU - Manual (Page 16)

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1-8 M32R-FPU Software Manual (Rev.1.01)
CPU PROGRAMMING MODEL
1.3 Control Registers
1.3.6 Floating-point Exceptions (FPE)
Floating-point Exception (FPE) occurs when Unimplemented Exception (UIPL) or
one of the five exceptions specified in the IEEE754 standard (OVF/UDF/IXCT/
DIV0/IVLD) is detected. Each exception processing is outlined below.
(1) Overflow Exception (OVF)
The exception occurs when the absolute value of the operation result exceeds the
largest describable precision in the floating-point format. The following table shows
the operation results when an OVF occurs.
Operation Result (Content of the Destination Register)
Rounding Mode Sign of the Result When the OVF EIT processing When the OVF EIT processing
is masked (Note 1) is executed (Note 2)
–infinity + +MAX
– –infinity
+infinity + +infinity
– –MAX No change
0 + +MAX
– –MAX
Nearest + +infinity
– –infinity
Note 1: When the Overflow Exception Enable (EO) bit (FPSR register bit 20) = "0"
Note 2: When the Overflow Exception Enable (EO) bit (FPSR register bit 20) = "1"
Note: • If an OVF occurs while EIT processing for OVF is masked, an IXCT occurs at the same time.
• +MAX = H'7F7F FFFF, –MAX = H'FF7F FFFF
(2) Underflow Exception (UDF)
The exception occurs when the absolute value of the operation result is less than
the largest describable precision in the floating-point format. The following table
shows the operation results when a UDF occurs.
Operation Result (Content of the Destination Register)
When UDF EIT processing is masked (Note 1) When UDF EIT processing is executed (Note 2)
DN = 0: An unimplemented exception occurs No change
DN = 1: 0 is returned
Note 1: When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "0"
Note 2: When the Underflow Exception Enable (EU) bit (FPSR register bit 18) = "1"