Renesas M32R-FPU - Manual (Page 173)

APPENDICES
APPENDICES-15 M32R-FPU Software Manual (Rev.1.01)
Appendix Figure 3.2.6 Pipeline Flow with Stalls (4)
<Case 8> The FPU and integer instructions run consecutively (with no register dependency)
IF D E WB
IF D WB E2
D WB E stall
IF D E2 WB E1
E1
stall
IF
<Case 9> The FPU and integer instructions run consecutively (with register dependency)
IF D E WB
IF D WB E2
D E stall stall
IF D WB E2 E1
E1
Bypass process
Bypass process
stall stall
IF
ADD R0,R1
ADD R5,R6
FADD R2,R3,R4
FADD R7,R8,R9
<Case 10> The FMADD/FMSUB instructions run consecutively with the integer instruction
(with no register dependency)
IF D E WB
IF D WB E2
D WB E stall stall
IF D E2 WB EM EA
EM EA
stall stall
IF
ADD R0,R1
ADD R5,R6
FMADD R2,R3,R4
FMADD R7,R8,R9
ADD R0 ,R1
ADD R0 ,R6
FADD R0 , R0 ,R4
FADD R0 , R0 ,R9
<Case 11> The FMADD/FMSUB instructions run consecutively with the integer instruction
(with register dependency)
IF D E WB
IF D WB E2 EA
D WB E stall stall stall
IF D WB E2 EM EA
EM
Bypass process
stall stall stall
IF
ADD R0 ,R1
ADD R0 ,R6
FMADD R0 , R0 ,R4
FMADD R0 ,R8,R9
WB
APPENDIX 3
Appendix 3 Pipeline Processing