Renesas M32R-FPU - Manual (Page 95)

3
3-57 M32R-FPU Software Manual (Rev.1.01)
INSTRUCTIONS
3.2 Instruction description
[Supplemental Operation Description]
The results of the FTOS instruction executed based on the Rsrc value, both when DN = 0 and DN = 1,
are shown in below.
DN = 0
Rsrc Value (exponent with no bias) Rdest Exception
Rsrc
≥ 0
+Infinity When EIT occurs: no change Invalid Operation Exception
127
≥
exp
≥
15 Other EIT: H'0000 7FFFF
14
≥
exp
≥
-126 H'0000 0000 to H'0000 7FFF No change (Note 1)
+Denormalized value No change Unimplemented Exception
+0 H'0000 0000 No change
Rsrc < 0 -0
-Denormalized value No change Unimplemented Exception
14
≥
exp
≥
-126 H'0000 0000 to H'FFFF 8001 No change (Note 1)
127
≥
exp
≥
15 When EIT occurs: no change Invalid Operation Exception
-Infinity Other EIT: H’FFFF 8000 (Note 2)
NaN QNaN When EIT occurs: no change Invalid Operation Exception
Other EIT:
SNaN Signed bit = 0:H’0000 7FFF
Signed bit = 1:H’FFFF 8000
Note 1: Inexact Exception occurs when rounding is performed.
2: Inexact Exception does not occur when Rsrc = H’CF00 0000.
DN = 1
Rsrc Value (exponent with no bias) Rdest Exception
Rsrc
≥ 0
+Infinity When EIT occurs: no change Invalid Operation Exception
127
≥
exp
≥
15 Other EIT: H'0000 7FFF
14
≥
exp
≥
-126 H'0000 0000 to H'0000 7FFF No change (Note 1)
+0, +Denormalized value H'0000 0000 No change
Rsrc < 0 -0, -Denormalized value
14
≥
exp
≥
-126 H'0000 0000 to H'FFFF 8001 No change (Note 1)
127
≥
exp
≥
15 When EIT occurs: no change Invalid Operation Exception
-Infinity Other EIT: H'FFFF 8000 (Note 2)
NaN QNaN When EIT occurs: no change Invalid Operation Exception
Other EIT:
SNaN Signed bit = 0:H’0000 7FFF
Signed bit = 1:H’FFFF 8000
Note 1: Inexact Exception occurs when rounding is performed.
2: No Exceptions occur when Rsrc = H’C700 0000. When Rsrc = H’C700 0001 to H’C700 00FF,
the Inexact Exception occurs and the Invalid Operation Exception does not occur.
FTOS FTOS floating point Instructions
Float to short
[M32R-FPU Extended Instruction]