Renesas M32R-FPU - Manual (Page 167)

APPENDICES
APPENDICES-9 M32R-FPU Software Manual (Rev.1.01)
The overview of each pipeline stage is shown below.
● IF stage (instruction fetch stage)
The instruction fetch (IF) is processed in this stage. There is an instruction queue
and instructions are fetched until the queue is full regardless of the completion of
decoding in the D stage.
If there is an instruction already in the instruction queue, the instruction read out
of the instruction queue is passed to the instruction decoder.
● D stage (decode stage)
Instruction decoding is processed in the first half of the D stage (DEC1).
T h e s u b s e q u e n t i n s t r u c t i o n d e c o d i n g ( D E C 2 ) a n d a r e g i s t e r f e t c h ( R F ) i s
processed in the second half of the stage.
● E stage (execution stage)
Operations and address calculations (OP) are processed in the E stage.
If an operation result from the previous instruction is required, bypass process
(BYP) is performed in the first half of the E stage.
● E1, EM, EA stage (execution stage)
These are the initial stages for execution of the FPU instructions. The EM and EA
stages only use instructions FMADD and FMSUB. All other instructions are used
in the E1stage
● E2 stage (execution stage)
This is the secondary stage for the execution of FPU instructions and mainly
rounding is performed.
● MEM stage (memory access stage)
Operand accesses (OA) are processed in the MEM stage. This stage is used only
when the load/store instruction is executed.
● WB stage (write back stage)
The operation results and fetched data are written to the registers in the WB
stage.
APPENDIX 3
Appendix 3 Pipeline Processing