1 processor status word register: psw (cr0), Cpu programming model, 3 control registers – Renesas M32R-FPU User Manual
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M32R-FPU Software Manual (Rev.1.01)
CPU PROGRAMMING MODEL
1.3 Control Registers
The Processor Status Word Register (PSW) indicates the M32R-FPU status. It
consists of the current PSW field which is regularly used, and the BPSW field where
a copy of the PSW field is saved when EIT occurs.
The PSW field consists of the Stack Mode (SM) bit, the Interrupt Enable (IE) bit and
the Condition (C) bit.
The BPSW field consists of the Backup Stack Mode (BSM) bit, the Backup Interrupt
Enable (BIE) bit and the Backup Condition (BC) bit.
At reset release, BSM, BIE and BC are undefined. All other bits are "0".
0
0
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
8
9
10
11
12
13
14
b15
b0
?
?
0
0
0
0
0
?
0
0
0
0
0
0
0
0
BC
SM
IE
C
23
24
25
26
27
28
29
30
b31
17
18
19
20
21
22
b16
BIE
BSM
BPSW field
0
0
PSW field
< At reset release: "B'0000 0000 0000 0000 ??00 000? 0000 0000 >
b
Bit Name
Function
R
W
0-15
No function assigned. Fix to "0".
0
0
16
BSM
Saves value of SM bit when EIT occurs
R
W
Backup SM Bit
17
BIE
Saves value of IE bit when EIT occurs
R
W
Backup IE Bit
18-22
No function assigned. Fix to "0".
0
0
23
BC
Saves value of C bit when EIT occurs
R
W
Backup C Bit
24
SM
0: Uses R15 as the interrupt stack pointer
R
W
Stack Mode Bit
1: Uses R15 as the user stack pointer
25
IE
0: Does not accept interrupt
R
W
Interrupt Enable Bit
1: Accepts interrupt
26-30
No function assigned. Fix to "0".
0
0
31
C
Indicates carry, borrow and overflow resulting
R
W
Condition Bit
from operations (instruction dependent)
1.3.1 Processor Status Word Register: PSW (CR0)