Renesas M32R-FPU - Manual (Page 112)

3
3-74 M32R-FPU Software Manual (Rev.1.01)
MULHI MULHI
DSP function instruction
Multiply high-order halfwords
[Mnemonic]
MULHI Rsrc1,Rsrc2
[Function]
Multiply
accumulator = (( signed) (Rsrc1 & 0xffff000 ) * (signed short) (Rsrc2 >> 16));
[Description]
MULHI multiplies the high-order 16 bits of Rsrc1 and the high-order 16 bits of Rsrc2, and
stores the result in the accumulator.
However, the LSB of the multiplication result is aligned with bit 47 in the accumulator, and the
portion corresponding to bits 0 through 15 of the accumulator is sign-extended. Bits 48 through
63 of the accumulator are cleared to 0. The high-order 16 bits of Rsrc1 and Rsrc2 are treated as
signed values.
The condition bit (C) is unchanged.
[EIT occurrence]
None
[Encoding]
MULHI Rsrc1,Rsrc2 src1 0011 src2 0000
Rsrc1 high-order 16 bits
Rsrc2 high-order 16 bits x
0 15 16 31
0
0 15 16 31 32 47 48 63
Value in accumulator after the
execution of the MALHI instruction
Sign extension
INSTRUCTIONS
3.2 Instruction description