Renesas M32R-FPU - Manual (Page 80)

3
3-42 M32R-FPU Software Manual (Rev.1.01)
INSTRUCTIONS
3.2 Instruction description
FDIV FDIV
[Mnemonic]
FDIV Rdest,Rsrc1,Rsrc2
[Function]
Floating-point divide
Rdest = Rsrc1 / Rsrc2 ;
[Description]
Divide the floating-point single precision value stored in Rsrc1 by the floating-point single pre-
cision value stored in Rsrc1 and store the result in Rdest. The result is rounded according to the
RM field of FPSR. The DN bit of FPSR handles the modification of denormalized numbers. The
condition bit (C) remains unchanged.
[EIT occurrence]
Floating-Point Exceptions (FPE)
• Unimplemented Operation Exception (UIPL)
• Invalid Operation Exception (IVLD)
• Overflow (OVF)
• Underflow (UDF)
• Inexact Exception (IXCT)
• Zero Divide Exception (DIV0)
[Encoding]
floating-point Instructions
Floating-point divide
[M32R-FPU Extended Instruction]
src1 1101 src2 0000 dest 0010 0000 0000
FDIV Rdest,Rsrc1,Rsrc2