Renesas M32R-FPU - Manual (Page 81)

3
3-43 M32R-FPU Software Manual (Rev.1.01)
INSTRUCTIONS
3.2 Instruction description
[Supplemental Operation Description]
The following shows the values of Rsrc1 and Rsrc2 and the operation results when DN = 0 and
DN = 1.
DN = 0
DN = 1
IVLD: Invalid Operation Exception
UIPL: Unimplemented Exception
DIV0: Zero Divide Exception
NaN: Not a Number
SNaN: Signaling NaN
QNaN: Quiet NaN
Rsrc2
divide
UIPL
QNaN
QNaN
SNaN
QNaN
SNaN
+0
+0
0
0
+0
+0
+Infinity
+Infinity
+Infinity
IVLD
DIV0
IVLD
IVLD
-Infinity
-Infinity
-Infinity
Infinity
-0
-0
-0
+Infinity
-Infinity
-0
Rsrc1
Normalized
Number
Normalized
Number
Denormalized
Number
Denormalized
Number
Rsrc2
QNaN
QNaN
SNaN
QNaN
SNaN
+0, +
+0, + -0, -
-0, -
+0
+0
+Infinity
+Infinity
+Infinity
Infinity
IVLD
DIV0
IVLD
IVLD
-Infinity
-Infinity
-Infinity
-0
-0
0
0
+Infinity
-Infinity
Rsrc1
Normalized Number
Normalized
Number
divide
Denormalized
Number
Denormalized
Number
Denormalized
Number
Denormalized
Number
FDIV FDIV floating point Instructions
Floating-point divide
[M32R-FPU Extended Instruction]