Renesas M32R-FPU - Manual (Page 177)

APPENDICES
APPENDICES-19 M32R-FPU Software Manual (Rev.1.01)
APPENDIX 5
Appendix 5 IEEE754 Specification Overview
Appendix Table 5.1.1 Single Precision Floating-Point Bit Values
Exponent Expressed value
Before adding bias After adding bias
( =0111 1111)
0111 1111 (+127) 1111 1110 Normalized number
• • • • • • (The absolute value can be described for the range
1000 0010 (-126) 0000 0001 of 1. 0…0 x 2 ^ -126 to 1. 1…1 x 2 ^ 127)
(1000 0001 (-127) ) 0000 0000 Fraction field = all 0:
±
0
Fraction field
≠
all 0: denormalized number
(1000 0000 (-128) ) 1111 1111 Fraction field = all 0:
±∞
Fraction field
≠
all 0: NaN (the value is split into SNaN and
QNaN according to the value of high-order bit of the
fraction field)
(1) Denormalized Numbers
Denormalized numbers represent numbers (values??) that have an absolute value
less than 1. 0…0 x 2 ^ -126. Single-precision denormalized numbers are expressed as
follows:
(-1) ^ s x 0.f x 2 ^ -126
(2) NaN (Not a Number)
SNaN (Signaling NaN): a NaN in which the MSB of the decimal fraction field is "0".
When SNaN is used as the source operand in an operation, an IVLD occurs. SNaNs
are useful in identifying program bugs when used as the initial value in a variable.
However, SNaNs cannot be generated by hardware.
QNaN (Quiet NaN): a NaN in which the MSB of the decimal fraction field is "1". Even
when QNaN is used as the source operand in an operation, an IVLD will not occur
(excluding comparison and format conversion). Because a result can be checked by
the arithmetic operations, QNaN allows the user to debug without executing an EIT
processing. QNaNs are created by hardware.