Renesas M32R-FPU - Manual (Page 150)

3
3-112 M32R-FPU Software Manual (Rev.1.01)
STH STH
load/store instruction
Store halfword
[M32R-FPU Extended Mnemonic]
[Mnemonic]
(1) STH Rsrc1,@Rsrc2
(2) STH Rsrc1,@Rsrc2+ [M32R-FPU Extended Mnemonic]
(3) STH Rsrc1,@(disp16,Rsrc2)
[Function]
Store
(1) * ( signed short *) Rsrc2 = Rsrc1;
(2) * ( signed short *) Rsrc2 = Rsrc1, Rsrc2 + = 2 ;
(3) * ( signed short *) ( Rsrc2 + ( signed short ) disp16 ) = Rsrc1;
[Description]
(1) STH stores the least significant halfword of Rsrc1 in the memory at the address specified
by Rsrc2.
(2) STH stores the LSB halfword of Rsrc1 to the memory of the address specified by Rsrc2,
and then increments Rsrc2 by 2.
(3) STH stores the least significant halfword of Rsrc1 in the memory at the address specified
by Rsrc combined with the 16-bit displacement. The displacement value is sign-ex-
tended to 32 bits before the address calculation.
The condition bit (C) is unchanged.
[EIT occurrence]
Address exception (AE)
[Encoding]
src1 1010
src1 0010 0010 src2
0010 src2 disp16
STH Rsrc1,@Rsrc2
STH Rsrc1,@(disp16,Rsrc2)
INSTRUCTIONS
3.2 Instruction description
src1 0010 0011 src2 STH Rsrc1,@Rsrc2+