Renesas M32R-FPU - Manual (Page 164)

APPENDICES
APPENDICES-6 M32R-FPU Software Manual (Rev.1.01)
mnemonic function condition bit (C)
NEG Rdest,Rsrc Rdest = 0 - Rsrc –
NOP /*no-operation*/ –
NOT Rdest,Rsrc Rdest = ~ Rsrc –
OR Rdest,Rsrc Rdest = Rdest | Rsrc –
OR3 Rdest,Rsrc,#imm16 Rdest = Rsrc | (uh)imm16 –
RAC Round the 32-bit value in the accumulator –
RACH Round the 16-bit value in the accumulator –
REM Rdest,Rsrc Rdest = (s)Rdest % (s)Rsrc –
REMU Rdest,Rsrc Rdest = (u)Rdest % (u)Rsrc –
RTE PC = BPC & 0xfffffffc, change
PSW[SM,IE,C] = PSW[BSM,BIE,BC]
SETH Rdest,#imm16 Rdest = imm16 << 16 –
SETPSW #imm8 PSW | = imm8&0x000000ff change
SLL Rdest,Rsrc Rdest = Rdest << (Rsrc & 31) –
SLL3 Rdest,Rsrc,#imm16 Rdest = Rsrc << (imm16 & 31) –
SLLI Rdest,#imm5 Rdest = Rdest << imm5 –
SRA Rdest,Rsrc Rdest = (s)Rdest >> (Rsrc & 31) –
SRA3 Rdest,Rsrc,#imm16 Rdest = (s)Rsrc >> (imm16 & 31) –
SRAI Rdest,#imm5 Rdest = (s)Rdest >> imm5 –
SRL Rdest,Rsrc Rdest = (u)Rdest >> (Rsrc & 31) –
SRL3 Rdest,Rsrc,#imm16 Rdest = (u)Rsrc >> (imm16 & 31) –
SRLI Rdest,#imm5 Rdest = (u)Rdest >> imm5 –
ST Rsrc1,@(disp16,Rsrc2) *(s *)(Rsrc2+(sh)disp16) = Rsrc1 –
ST Rsrc1,@+Rsrc2 Rsrc2 += 4, *(s *)Rsrc2 = Rsrc1 –
ST Rsrc1,@-Rsrc2 Rsrc2 -= 4, *(s *)Rsrc2 = Rsrc1 –
ST Rsrc1,@Rsrc2 *(s *)Rsrc2 = Rsrc1 –
STB Rsrc1,@(disp16,Rsrc2) *(sb *)(Rsrc2+(sh)disp16) = Rsrc1 –
STB Rsrc1,@Rsrc2 *(sb *)Rsrc2 = Rsrc1 –
STH Rsrc1,@(disp16,Rsrc2) *(sh *)(Rsrc2+(sh)disp16) = Rsrc1 –
STH Rsrc1,@Rsrc2 *(sh *)Rsrc2 = Rsrc1 –
STH Rsrc1,@Rsrc2+ *(sh *)Rsrc2 = Rsrc1, Rsrc2 += 2 –
SUB Rdest,Rsrc Rdest = Rdest - Rsrc –
SUBV Rdest,Rsrc Rdest = Rdest - Rsrc change
SUBX Rdest,Rsrc Rdest = Rdest - Rsrc - C change
TRAP #n PSW[BSM,BIE,BC] = PSW[SM,IE,C] change
PSW[SM,IE,C] = PSW[SM,0,0]
Call trap-handler number-n
UNLOCK Rsrc1,@Rsrc2 if(LOCK) { *(s *)Rsrc2 = Rsrc1; } LOCK=0 –
UTOF Rdest,Rsrc Rdest = (float)(unsigned int) Rsrc; –
XOR Rdest,Rsrc Rdest = Rdest ^ Rsrc –
XOR3 Rdest,Rsrc,#imm16 Rdest = Rsrc ^ (uh)imm16 –
APPENDIX 2
Appendix 2 Instruction List