Renesas M32R-FPU - Manual (Page 15)

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1-7 M32R-FPU Software Manual (Rev.1.01)
CPU PROGRAMMING MODEL
1.3 Control Registers
21 EV 0: Mask EIT processing to be executed when an R W
Invalid Operation Exception invalid operation exception occurs
Enable Bit 1: Execute EIT processing when an invalid
operation exception occurs
22 No function assigned. Fix to "0". 0 0
23 DN 0: Handle the denormalized number as a R W
Denormalized Number Zero denormalized number
Flash Bit (Note 2) 1: Handle the denormalized number as zero
24 CE 0: No unimplemented operation exception occurred . R (Note 3)
Unimplemented Operation 1: An unimplemented operation exception occurred.
Exception Cause Bit When the bit is set to "1", the execution of an
FPU operation instruction will clear it to "0".
25 CX 0: No inexact exception occurred. R (Note 3)
Inexact Exception Cause 1: An inexact exception occurred.
Bit When the bit is set to "1", the execution of an
FPU operation instruction will clear it to "0".
26 CU 0: No underflow exception occurred. R (Note 3)
Underflow Exception Cause 1: An underflow exception occurred.
Bit When the bit is set to "1", the execution of an
FPU operation instruction will clear it to "0".
27 CZ 0: No zero divide exception occurred. R (Note 3)
Zero Divide Exception 1: A zero divide exception occurred.
Cause Bit When the bit is set to "1", the execution of an
FPU operation instruction will clear it to "0".
28 CO 0: No overflow exception occurred. R (Note 3)
Overflow Exception 1: An overflow exception occurred.
Cause Bit When the bit is set to "1", the execution of an
FPU operation instruction will clear it to "0".
29 CV 0: No invalid operation exception occurred. R (Note 3)
Invalid Operation Exception 1: An invalid operation exception occurred.
Cause Bit When the bit is set to "1", the execution of an
FPU operation instruction will clear it to "0".
30, 31 RM 00: Round to Nearest R W
Rounding Mode Selection Bit 01: Round toward Zero
10: Round toward +Infinity
11: Round toward -Infinity
Note 1: ‘If EIT processing is unexecuted’ means whenever one of the exceptions occurs, enable bits
17 to 21 are set to "0" which masks the EIT processing so that it cannot be executed. If two
exceptions occur at the same time and their corresponding exception enable bits are
set differently (one enabled, and the other masked), EIT processing is executed. In this
case, these two flags do not change state regardless of the enable bit settings.
Note 2: If a denormalized number is given to the operand when DN = "0", an unimplemented
exception occurs.
Note 3: This bit is cleared by writing "0". Writing "1" has no effect (the bit retains the value it had
before the write).