Renesas M32R-FPU - Manual (Page 182)

APPENDICES
APPENDICES-24 M32R-FPU Software Manual (Rev.1.01)
(1) Overflow occurs in Step 1
<When EO = 0, EX = 0: OVF and IXCT occur>
Type of R0 Condition FMUL + FADD Operation FMADD Operation
Normalized – R0 = OVF immediate R0 = OVF immediate
number, 0 value (Note 1) + R0 value (Note 2)
Infinity when OVF immediate value EV=0 IVLD occurs same as left
R0=H'7FFF FFFF
is R0 and the opposite sign EV=1 IVLD occurs, EIT occurs same as left
of the infinity sign R0 = maintained
factors other than above – R0 =
∞
same as left
(same as original value)
Denormalized DN=0 UIPL occurs, EIT occurs same as left
number R0 = maintained
DN=1 R0 = OVF immediate value same as left
(Note 1)
QNaN – R0 = maintained (QNaN) same as left
SNaN EV=0 IVLD occurs same as left
R0 = R0 converted to QNaN
EV=0 IVLD occurs, EIT occurs same as left
R0 = maintained (SNaN)
Note 1: Refer to [Appendix Table 5.3.1 Operation Result due to OVF Exception] for immediate
values if an overflow occurs due to Overflow Exclusion when the EIT processing is
masked.
Note 2: In Step 1, the rounding mode is set to [Round toward 0]. However, when an overflow
occurs, the immediate value is rounded according to the rounding mode. Refer to
[Appendix Table 5.3.1 Operation Result due to OVF Exception] for these values.
However, when the rounding mode is [round toward nearest], the OVF immediate value =
infinity and the R0 value becomes the same as that of FMUL + FADD.
<When EO = 1: OVF occurs>
Type of R0 Condition FMUL + FADD Operation FMADD Operation
Normalized – EIT occurs when FMUL is EIT occurs,
number, 0, completed R0 = maintained
Infinity R0 = maintained
Denormalized DN=0 Same as above UIPL occurs,
number EIT occurs
R0 = maintained
DN=1 Same as above EIT occurs
R0 = maintained
QNaN – Same as above Same as above
SNaN EV=0 Same as above IVLD occurs,
EIT occurs
R0 = maintained
EV=1 Same as above Same as above
APPENDIX 6
Appendix 6 M32R-FPU Specification Supplemental Explanation