Renesas M32R-FPU - Manual (Page 26)

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2-2 M32R-FPU Software Manual (Rev.1.01)
2.1 Instruction set overview
The M32R-FPU has a total of 100 instructions. The M32R-FPU has a RISC architecture.
Memory is accessed by using the load/store instructions and other operations are
executed by using register-to-register operation instructions.
M32R CPU supports compound instructions such as " load & address update" and "store
& address update" which are useful for high-speed data transfer.
2.1.1 Load/store instructions
The load/store instructions carry out data transfers between a register and a memory.
LD Load
LDB Load byte
LDUB Load unsigned byte
LDH Load halfword
LDUH Load unsigned halfword
LOCK Load locked
ST Store
STB Store byte
STH Store halfword
UNLOCK Store unlocked
INSTRUCTION SET
2.1 Instruction set overview