FANUC Robotics America V7865* - Manual (Page 59)

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VME Bridge
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VME, prior to doing writes to the Tsi148. (Note, please see the Tsi148 Manual and
Errata regarding the requirements to use the DWB bit of the Tsi148). The user may
also implement other methods of gaining ownership of the VME, such as Tsi148
semaphores. But, regardless of the method used, when using shared memory, the user
must gain exclusive VME ownership prior to generating asynchronous VME writes.
Extremely Long VME Slave Response Time : VME slave devices (or VME BERR
conditions) that have a DTAK (or BERR) response time of greater than 16μs can cause
Bridge Ordering rule issues with intermixed reads and writes through the Tsi148. If
the SBC user wishes to do an extended number (larger than the depth of the Tsi148
write post buffer) of consecutive writes from the processor to the VME through the
Tsi148, and those writes can be intermixed with reads from another task, then the user
must verify that all slaves within the system have DTACK response time of less than
16μs, and that the VME BERR timer of the system is set to 16μs max. Also it is
suggested that prior to doing any large VME transfer, the users should first request
ownership of the VME through the DWB Bit in the Tsi148, and be granted the VME,
prior to doing writes to the Tsi148. (Note, please see the Tsi148 Manual and Errata
regarding the requirements to use the DWB bit of the Tsi148). The user may also
implement other methods of gaining ownership of the VME, such as Tsi148
semaphores. But, regardless of the method used, when generating an extended
number of consecutive processor to VME writes (larger than the depth of the Tsi148
write post buffer), the user must gain exclusive VME ownership prior to generating
these asynchronous VME writes.
NOTE : Failure to implement the procedures outlined above may cause some system
implementations to lockup or generate unwanted VME errors.