FIC A360 - Manual (Page 108)

Hardware Functional Overview
The integrated L2 cache is designed to help improve performance, and it complements the
system bus by providing critical data faster and reducing total system power consumption.
The Pentium III processor’s 64-bit wide Gunning Transceiver Logic (GTL+) system bus
provides a glue-less, point-to-point interface for an I/O bridge/memory controller.
Features summary of the Pentium-III CPU:
• Processor core/bus speeds
- Featuring Intel SpeedStep technology: Maximum Performance Mode at 1.60V
and Conserved Performance Mode at 1.35V
• Supports the Intel Architecture with Dynamic Execution
• On-die primary (L1) 16-Kbyte instruction cache and 16-Kbyte write-back data cache
• On-die second level L2 cache (256-Kbyte)
• Integrated GTL+ termination
64-bit data bus, 100-MHz operation
• Integrated math co-processor
• Intel Processor Serial Number
• Fully compatible with previous Intel microprocessors
- Binary compatible with all applications
- Support for MMX technology
- Support for Streaming SIMD Extensions enhances floating point, video, sound,
and 3-D application performance
• Power Management Features
- Quick Start for low power, low exit latency clock “throttling”
- Deep Sleep mode provide low power dissipation
• On-die thermal diode
4.4.2 Intel Celeron Features
The Intel Celeron processor is designed for uni-processor based Value PC and is binary
compatible with previous generation Intel architecture processors. The Intel Celeron
processor provides good performance for applications running on advanced operating systems
such as Windows 98 / Me, Windows NT / 2000, and UNIX. This is achieved by integrating
the best attributes of Intel processors – the dynamic execution performance of the P6 micro-
architecture plus the capabilities of MMX technology – bringing a balanced level of
performance to the Value PC market segment.
Features summary of the Celeron CPU:
• Available up to 700 MHz core frequencies
• Integrated primary (L1) 16-Kbyte instruction cache and 16-Kbyte write back data cache
• Integrated second level (L2) cache 128-Kbyte ECC protected cache data array
• Intel’s latest Celeron processors in the FC-PGA package are manufactured using the
advanced 0.18 micron technology.
• Binary compatible with applications running on previous members of the Intel
microprocessor line.
• Supports the Intel Architecture with Dynamic Execution
• Specifically designed for uni-processor based Value PC systems, with the capabilities of
MMX technology.
• Power Management Features. Quick Start for low power, low exit latency clock
“throttling” and Deep Sleep mode for extremely low power dissipation.
• Optimized for 32-bit applications running on advanced 32-bit operating systems.
4-4
FIC A360 Service Manual