FIC A360 - Manual (Page 76)

Software Functional Overview
FIC A360 Service Manual
3-19
Sleeping State Definitions
Sleeping states (Sx states) are types of sleeping states within the global sleeping state,
G1. The Sx states are briefly defined below. For a detailed definition of the system
behavior within each Sx state, refer to ACPI specification section 7.5.2. For a detailed
definition of the transitions between each of the Sx states, refer to ACPI specification
section 9.1.
S1 Sleeping State:
The S1 sleeping state is a low wake-up latency sleeping state. In this state, no system context
is lost (CPU or chip set) and hardware maintains all system context.
S2 Sleeping State:
The S2 sleeping state is a low wake-up latency sleeping state. This state is similar to the S1
sleeping state except the CPU and system cache context is lost (the OS is responsible for
maintaining the caches and CPU context). Control starts from the processor’s reset vector
after the wake-up event.
S3 Sleeping State:
The S3 sleeping state is a low wake-up latency sleeping state where all system context is lost
except system memory. CPU, cache, and chip set context are lost in this state. Hardware
maintains memory context and restores some CPU and L2 configuration context. Control
starts from the processor’s reset vector after the wake-up event.
S4 Sleeping State:
The S4 sleeping state is the lowest power, longest wake-up latency sleeping state supported
by ACPI. In order to reduce power to a minimum, it is assumed that the hardware platform
has powered off all devices. Platform context is saved in disk.
S5 Soft Off State:
The S5 state is similar to the S4 state except the OS does not save any context nor enable
any devices to wake the system. The system is in the “SOFT” off state and requires a
complete boot when awakened. Software uses a different state value to distinguish between
the S5 state and the S4 state to allow for initial boot operations within the BIOS to
distinguish whether or not the boot is going to wake from a saved memory image.
3.5.2 System Power Plane
The system components are grouped as the following parties to let the system to control the
On/Off of power under different power management modes.
The power plane is divided as following:
Power Group Power Control Pin Controlled Devices
B+ Nil IMM, (9V~12V)
+3VA Nil PIC16C62A, VT82C686B(RTC I/F), Internal
Modem, PMU07
+12V PWRON PCMCIA card , AC97 codec
+5V PWRON PCMCIA Slot 5V
+3V PWRON VGA, PCMCIA, PCMCIA Slot 3V, DRAM,
Twister(DRAM I/F), M38867, MAX3243
+5VS SUSB# Flash ROM, HDD, CD-ROM, USB, Internal K/B,
Glide Pad, External PS/2 Mouse, Audio AMP,