FIC A360 - Manual (Page 99)

Software Functional Overview
3-42
FIC A360 Service Manual
Register Bit Number
Function Address
Name
R/W
7 6 5 4 3 2 1 0
Logic Default Description
A0h
*3
ADP_STS R(/W) RES[7:1]
C
O
N
- - CON = 1 : AC adapter is connected
A1h
*3
BAT1_STS
(1st Battery)
R(/W) - -
A2h
*3
BAT2_STS
(2
nd Battery)
R(/W)
B
T
P E
M
P
L
O
W
W
A
R
E
R
R
D
C
H
G
C
H
G C
O
N
- -
BTP =1:
EMP =1:
LOW =1:
WAR=1:
ERR =1:
DCHG=1:
CHG=1:
CON=1:
Battery trip point is
detected.
Battery is empty.
Battery is Low battery
state.
Battery is Warning state.
Battery is Error state.
Battery is discharged.
Battery is charged.
Battery is connected.
A3h
*3
Reserved R/W Don’t care - -
A4h
*3
BAT1_CAP R(/W) BCAP - -
A5h
*3
BAT2_CAP R(/W) BCAP - -
0x00-0x64 = 0-100(%)
0x7F = Unknown
0x80 = Not installed
A6h
*3
Reserved R/W Don’t care - -
A7h
SMB_Alert_
ADDR
R/W ADDRESS[6:0]
R
E
S
- 0x00
SMBAlert output device address
The alert response function is
available when this register is cleared
(0x00) only.
When the several devices assert the
alert signal at the same time, the least
address is stored to this register. And
when this register is cleared , next
alert address is stored to this register.
A8h
*5
GPIO-A_
EVT_STS
R/W STS_A [7:0] 0x00
A9h
*5
GPIO-B_
EVT_STS
R/W 0 STS_B [6:0] 0x00
AAh
*5
GPIO-C_
EVT_STS
R/W 0 0 0 0 0 0
STS
_C
[1:0]
Read
0:No event
1:EVT
detection
Write
0:Clear
event
1:Ignore
0x00
To clear the notified event flag without
unexpected event loss, clear the
corresponding bit flag only.
For this operation, this register has
special writing manner as follows.
STS_X
 (STS_X) AND (Written
data)
ABh
*5
RUN_
EVT_STS
R/W 0x00
ACh
*5
WAKE_
EVT_STS
R/W
B
T
P
2
S
M
B
A
L
R
T
G
P
I
O
R
E
S
B
A
T
2
B
A
T
1
A
D
P
0x00
BTP2 =1:
SMB =1 :
ALRT=1 :
GPIO =1 :
BATn=1 :
ADP =1 :
TH =1 :
HIGH=1 :
LOW =1 :
ERR =1 :
BTP2 event is detected
SMBus event is detected.
SMBAlert is detected.
GPIO event is detected.
Battery event is detected.
Battery event is detected.
Thermal event is detected
High alarm point is
detected.
Low alarm point is
detected.
Polling communication
failure with retry.
ADh
*5
RUN_
EVT_STS_2
R/W Reserved [7:1]
T
H
0x00
AEh
*5
WAKE
EVT_STS_2
R/W Reserved [7:1]
T
H
0x00
Status
AFh
*5
THERMAL_
EVT_STS
R/W
Reserved
[7:3]
E
R
R L
O
W
H
I
G
H
Read
0:No event
1:EVT
detection
Write
0:Clear
event
1:Ignore
0x00
To clear the notified event flag without
unexpected event loss, clear the
corresponding bit flag only.
For this operation, this register has
special writing manner as follows.
STS_X
 (STS_X) AND (Written
data)
*3: This register is not cleared if the system is in S4-S5 state.
*5: After writing to this register, Set the “00h” to the BURST_FLG_CLR register.
R(/W): This is the read only register, but the written data will be able to read back till PMU
updates the data periodically, or PMU detects the status change.