Motorola ATCA-717 - Manual (Page 140)

Maps and Registers FPGA Registers
140 PENT/ATCA−717
S Reset mask register (index address 0x01)
The reset source register stores the source of the most recent reset. A write access clears
this register.Each bit is associated with one reset source. If the bit is set to one, the
corresponding reset has occurred. After a reset has occurred, this register should be
cleared. Otherwise, after the next reset of another source, more than one bit is set and you
may not be able to determine the most recent reset source.
a
Table 23: Reset Source Register
Bit Signal Description Default Access
0 PWR_ON 0: No reset
1: Power−on reset 1
2
r/w
1 WDG_RES 0: No reset
1: Watchdog reset 0
2
r/w
2 PB_RES 0: No reset
1: Face plate push button reset 0
2
r/w
3 PMC_RST 0: No reset
1: PMC slots reset 0
2
r/w
4 RTM_RES 0: No reset
1: RTM reset 0
2
r/w
5 CPU_RST 0: No reset
1: CPU reset issued by Host
Bridge 0
2
r/w
6 PCI_RES 0: No reset
1: Legacy PCI bus reset 0
2
r/w
7 IPMI_RES 0: No reset
1: IPMC building block reset 0
2
r/w
The reset mask register allows to enable/disable particular resets. If a bit is set, the
corresponding reset is enabled, otherwise it is disabled.
a
Note: a IPMC, legacy PCI and power−on reset cannot be enabled/disabled via this
register. a
Table 24: Reset Mask Register
Bit Signal Description Default Access
0 − Reserved 0
2
r
1 WDG_RES Watchdog reset
0: Disabled
1: Enabled 1
2
r/w