National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ - Manual (Page 161)

Appendix E Register-Level Programming
© National Instruments Corporation E-5 Lab-PC+ User Manual
Clearing the Analog Input Circuitry
The analog input circuitry can be cleared by writing to the A/D Clear Register, which leaves the
analog input circuitry in the following state:
• Analog input error flags OVERFLOW and OVERRUN are cleared.
• Pending interrupt requests are cleared.
• A/D FIFO has one garbage word of data.
Empty the A/D FIFO before starting any A/D conversions by performing two 8-bit reads on the
A/D FIFO Register and ignoring the data read. This operation guarantees that the A/D
conversion results read from the A/D FIFO are the results from the initiated conversions rather
than leftover results from previous conversions.
To clear the analog input circuitry and the A/D FIFO, complete these steps:
• Write 0 to the A/D Clear Register (8-bit write).
• Read the A/D FIFO Register twice and ignore the data (8-bit read).
Programming Multiple A/D Conversions on a Single
Input Channel
A sequence of timed A/D conversions is referred to in this manual as a data acquisition
operation. Two types of data acquisition operations are available on the Lab-PC+:
• Controlled acquisition mode
• Freerun acquisition mode
In controlled acquisition mode, two counters (Counters A0 and A1) are required for a data
acquisition operation. Counter A0 is used as a sample interval counter, while Counter A1 is used
as a sample counter. In this mode, a specified number of conversions are performed, after which
the hardware shuts off the conversions. Counter A0 generates the conversion pulses, and
Counter A1 gates off Counter A0 after the programmed count has expired. The number of
conversions in a single data acquisition operation in this case is limited to a 16-bit count (on
65,535).
In freerun acquisition mode, only one counter is required for a data acquisition operation.
Counter A0 continuously generates the conversion pulses as long as GATEA0 is held at a high
logic level. The software keeps track of the number of conversions that have occurred and turns
off Counter A0 after the required number of conversions have been obtained. The number of
conversions in a single data acquisition operation in this case is unlimited. Counter A0 is
clocked by a 1 MHz clock on start up.