Figure 3-10, Posttrigger data acquisition timing case 1, Figure 3-11 – National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual
Page 53: Posttrigger data acquisition timing case 2
Signal Connections
Chapter 3
Lab-PC+ User Manual
3-22
© National Instruments Corporation
and 3-11 illustrate two possible posttrigger data acquisition timing cases. In Figure 3-10, the
rising edge on EXTTRIG is sensed when the EXTCONV* input is high. Thus, the first A/D
conversion occurs on the second falling edge of EXTCONV*, after the rising edge on
EXTTRIG. In Figure 3-11, the rising edge on EXTTRIG is sensed when the EXTCONV* input
is low. In this case, the first A/D conversion occurs on the first falling edge of EXTCONV*,
after the rising edge on EXTTRIG. Notice that Figures 3-10 and 3-11 show a controlled
acquisition mode data acquisition sequence; that is, Sample Counter A1 disables further A/D
conversions after the programmed count (3 in the examples shown in Figures 3-10 and 3-11)
expires. The counter is not loaded with the programmed count until the first falling edge
following a rising edge on the clock input; therefore two extra conversion pulses are generated as
shown in Figures 3-10 and 3-11. EXTTRIG can also be used as an external trigger in freerun
acquisition mode.
tw 50 nsec minimum
EXTTRIG
EXTCONV*
CONVERT
V
IH
V
IL
tw
tw
Sample
Counter
X
X
3
2
1
0
Figure 3-10. Posttrigger Data Acquisition Timing Case 1
tw 50 nsec minimum
EXTTRIG
V
IH
V
IL
tw
EXTCONV*
CONVERT
td 50 nsec minimum
tw
Sample
Counter
X
3
2
1
0
Figure 3-11. Posttrigger Data Acquisition Timing Case 2