National Instruments Low-Cost Multifunction I/O Board for ISA Lab-PC+ User Manual
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Appendix E
Register-Level Programming
© National Instruments Corporation
E-11
Lab-PC+ User Manual
External Timing Considerations for Multiple
A/D Conversions
Two external timing signals, EXTTRIG and EXTCONV*, can be used for multiple A/D
conversions. EXTTRIG can be used to initiate a conversion sequence (posttrigger mode) or to
terminate an ongoing conversion sequence (pretrigger mode), and the EXTCONV* signal can be
used to time the individual A/D conversions from an external timing source. Chapter 3, Signal
Connections, contains the EXTTRIG and EXTCONV* signal specifications. The posttrigger and
pretrigger modes are described later in this appendix.
EXTCONV* is available on the 50-pin I/O connector to allow conversion to be controlled by an
external source. A conversion occurs whenever an active-low pulse (the pulse width is 250 ns
minimum) is detected on this TTL level line. EXTCONV* can be used for both single-channel
conversion sequences and multiple-channel scanning sequences. The programming steps are
similar to internal timing conversions except that Counter A0 is not used and its output should be
high, and OUT1 of Counter A1 must be forced low. After setting the SWTRIG bit, the first
EXTCONV* pulse starts the external conversion operation, but does not cause the A/D
conversion; the second pulse starts the first A/D conversion.
Using the EXTTRIG Signal to Initiate a Multiple A/D Conversion Data
Acquisition Operation (Posttrigger Mode)
If both the PRETRIG bit and the SWTRIG bit are cleared, and the HWTRIG bit is set in
Command Register 2, EXTTRIG functions as a start trigger for a multiple A/D conversion data
acquisition operation. In this mode, referred to as posttriggering, the sample interval counter is
gated off until a low-to-high edge is sensed on EXTTRIG. No samples are collected until
EXTTRIG makes its low-to-high transition. Transitions on the EXTCONV* line are also
ignored until a low-to-high edge is sensed on EXTRIG followed by a low-to-high edge on
EXTCONV* input.
Using the EXTTRIG Signal to Terminate a Multiple A/D Conversion Data
Acquisition Operation (Pretrigger Mode)
If the PRETRIG bit is set and the HWTRIG bit is cleared in Command Register 2, EXTTRIG
functions as a stop trigger for a multiple A/D conversion data acquisition operation. In this
mode, referred to as pretriggering, the sample counter is gated off until a low-to-high edge is
sensed on EXTTRIG. Counter A0 (the sample interval counter) starts as soon as the SWTRIG
bit is set. However, Counter A1, the sample counter, does not start counting until the first rising
edge on EXTTRIG. In this way, data is collected before the actual trigger rising edge. After the
rising edge occurs, the number of points specified in Counter A1 are collected and the acquisition
stops. You must allocate sufficient array space for all of the data, and specify both the number of
points and the indeterminate number of points that may be collected before the pretrigger signal
arrives. Alternatively, a circular buffer can be set up by the acquisition software so that data is
repeatedly loaded into the same section of memory. Although this method does not require an
indeterminate amount of memory, you can examine only samples acquired during a limited time
period before and after the trigger occurs. Pretriggering is set up by setting PRETRIG in
Command Register 2. PRETRIG supersedes HWTRIG; if both bits are set, then pretriggering is
enabled.